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36Kr Exclusive | AI Chip Processor IP Company Completes Nearly 100 Million Yuan Financing, Core Team from Top Semiconductor Companies like Synopsys, ARM 36氪首发 | AI芯片处理器IP公司完成近亿元融资,核心团队来自Synopsys、ARM等顶尖半导体公司

When nearly ten institutions, including Infinity Capital and Baiyun Jinkong, pour nearly a hundred million yuan into Sunayu Tech—a company that has only been established for a year—it’s more than just an investment; it feels like a collective vote on the anxiety gripping the current semiconductor industry. Everyone is searching for a solution to the core contradiction: AI models are evolving faster than chip design can keep up. Sunayu’s proposed remedy is “RISC-V + DSA,” paired with a self-devel 当英飞尼迪资本、白云金控等近十家机构把近亿元资金砸向成立刚满一年的隼瞻科技时,这不仅是一笔投资,更像是对当前半导体行业焦虑的一次集体投票——大家都在找那个能解决“AI模型越来越快,但芯片设计跟不上”这一核心矛盾的药方。隼瞻开出的药方是“RISC-V+DSA”,配上自研的EDA工具链,试图把过去只有芯片巨头才玩得转的专用处理器设计,变成一个“IP货架选购+平台自动生成”的平民游戏。

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When nearly ten institutions, including Infinity Capital and Baiyun Jinkong, pour nearly a hundred million yuan into Sunayu Tech—a company that has only been established for a year—it’s more than just an investment; it feels like a collective vote on the anxiety gripping the current semiconductor industry. Everyone is searching for a solution to the core contradiction: AI models are evolving faster than chip design can keep up. Sunayu’s proposed remedy is “RISC-V + DSA,” paired with a self-developed EDA toolchain. Their aim is to transform specialized processor design—a domain once exclusive to chip giants—into a democratized process of “selecting from an IP shelf and generating through a platform.”

The core of this story is compelling: as AI models become increasingly vertical, chips are being pushed from being “universal glue” to “specialized building blocks.” Running large models on traditional CPUs is like using an abacus to solve differential equations—technically possible, but painfully inefficient, to the point of making even Jensen Huang shake his head. Thus, specialized processors like NPUs and TPUs emerge. However, a new problem arises: customer models vary widely—from image recognition today to genome sequencing tomorrow. Designing a custom ASIC for each would be prohibitively expensive in both cost and time. The philosophy of DSA (Domain-Specific Architecture) is: “Stop forcing it—let the architecture adapt to the model, not the other way around.” This logic sounds flawless, but as always, the devil lies in the details of implementation.

Sunayu’s founder, Zeng Yi, pinpointed the pain point: building a medium-scale DSA processor traditionally requires 30 engineers working for six months. This isn’t chip design; it’s more like civil engineering. Their platform, ArchitStudio, claims to compress this cycle to 3 people over 3 weeks—if true, it would be a “nuclear bomb” in the chip industry, completely leveling the design barrier. But the issue is precisely that this sounds almost too good to be true, like science fiction. Processor design involves architecture, verification, and toolchains; each step is a complex systems engineering challenge. Claiming to “automatically generate RTL and toolchains” reminds me of those low-code platforms that promise “one-click app creation,” which often end up being toys for professionals. The real core competency may not lie in the intelligence of the tool itself, but in the accumulated deep understanding of domain algorithms and hardware-software synergy. This requires time and real-world scenarios to nurture—it cannot be rushed just by writing elegant code.

Choosing RISC-V as the foundation is a wise but risky move. Its open-source nature, extensibility, and zero licensing fees make it especially attractive in the AI era, particularly compared to ARM’s expensive licensing and strict restrictions. RISC-V is like the Linux of chip design: its ecosystem is still in a wild-growth phase, full of opportunities but equally filled with pitfalls. Sunayu’s task goes beyond just providing IP; they aim to establish a reliable design methodology and tool standard within the fragmented RISC-V world. Their mention of “reserving programmable space” is a defensive design for AI model’s rapid iteration, but this feels more like a hopeful wish. Once a chip is taped out, its hardware functionality is largely fixed. Can that reserved “space” truly keep pace with entirely new neural network architectures that might emerge three years from now? This is more of a bet on the continuity of technological trajectories.

Looking at their business model: standardized IP licensing, DSA solutions, and multi-core platform customization. These three lines seem comprehensive, but fundamentally, it’s still a “selling shovels” business. In the winner-takes-all brutality of the chip industry, selling shovels is safe, but both profit ceilings and customer loyalty are concerns. Especially facing EDA giants like Synopsys and Cadence, as well as numerous competitors eyeing the DSA market, Sunayu’s “all-in-one” advantage needs strong execution and proven customer success stories to back it up. They mention having deployments in communications, security, and automotive sectors—this is positive news, but who the specific customers are and what the performance data show will be the real indicators of whether this “shovel” is truly sharp.

At its core, Sunayu’s story is an attempt to use a software-platform mindset to deconstruct the complexity of hardware design. This is an ambitious vision that hits an industry pain point. But the chip industry has never been a place where “the fast fish eats the slow fish”; it values time, reliability, and ultimately, product capability. Securing nearly a hundred million in funding is just an entry ticket. The real test lies in whether they can prove, under the shadows of giants like ARM and Synopsys, that “AI-driven democratization of chip design” is not just a beautiful fantasy but a practical, deployable生产力. What the market lacks now is not concepts, but the ability to solder concepts to the physical world. Sunayu now has capital and a reasonably experienced team. What comes next depends on how they answer this most practical of questions.

当英飞尼迪资本、白云金控等近十家机构把近亿元资金砸向成立刚满一年的隼瞻科技时,这不仅是一笔投资,更像是对当前半导体行业焦虑的一次集体投票——大家都在找那个能解决“AI模型越来越快,但芯片设计跟不上”这一核心矛盾的药方。隼瞻开出的药方是“RISC-V+DSA”,配上自研的EDA工具链,试图把过去只有芯片巨头才玩得转的专用处理器设计,变成一个“IP货架选购+平台自动生成”的平民游戏。

这个故事的内核很性感:AI模型垂直化,逼得芯片从“万能胶水”走向“专用积木”。传统CPU跑大模型就像用算盘算微分方程,不是不能算,是姿势太难看,效率低到让黄仁勋都摇头。于是NPU、TPU这些专用处理器粉墨登场,但新问题来了:不同客户的模型千差万别,今天你做图像识别,明天他做基因测序,如果每个ASIC都从头设计,成本和时间根本耗不起。DSA(领域专用架构)的哲学就是“别折腾了,让架构去适配模型,而不是反过来”。这逻辑听起来无懈可击,但魔鬼向来藏在工程化的细节里。

隼瞻的创始人曾轶点出了痛点:一个中等规模的DSA处理器,传统模式需要30个工程师干半年。这哪是做芯片,简直是搞土木工程。而他们的平台ArchitStudio号称能把周期压缩到3人3周——如果这是真的,那简直是芯片界的“核弹”,直接把设计门槛炸平了。但问题恰恰在于,这听起来好得有点像科幻。处理器设计涉及架构、验证、工具链,每一步都是复杂系统工程。号称“自动生成RTL和工具链”,这让我想起那些承诺“一键生成APP”的低代码平台,最终往往沦为给专业人士打下手的玩具。真正的核心壁垒,或许不在工具本身的智能程度,而在于背后积累的、对各种领域算法和硬件协同的深刻理解。这需要时间和场景去喂养,不是代码写得漂亮就能速成的。

选择RISC-V作为底座,是明智但也冒险的一步。开源、可扩展、免授权费,这些优点在AI时代格外诱人,尤其是面对ARM高昂的授权费和严格的限制。RISC-V就像芯片设计的Linux,生态还在野蛮生长阶段,机会巨大,但坑也巨多。隼瞻要做的不只是提供IP,更是要在碎片化的RISC-V世界里,建立起一套可靠的设计方法论和工具标准。他们的“预留可编程空间”的说法,是对AI模型快速迭代的防御性设计,但这更像是一个美好的愿望。芯片一旦流片,硬件功能就基本固定,预留的“空间”是否真的能跟上三年后可能出现的全新神经网络架构?这更多是在赌技术路线的延续性。

再看他们的商业模式:标准化IP授权、DSA方案、多核平台定制。三条线看似全面,但本质上还是“卖铲子”的生意。在芯片这个赢家通吃的残酷游戏里,卖铲子固然稳妥,但利润天花板和客户忠诚度都是问题。尤其是面对Synopsys、Cadence这些EDA巨头,以及众多垂涎DSA市场的同行,隼瞻的“一体化”优势需要极强的执行力和客户成功案例来证明。他们提到已在通信、安全、汽车等领域落地,这是好消息,但具体客户是谁、性能数据如何,才是判断这把“铲子”是否真的锋利的关键。

本质上,隼瞻的故事是试图用软件平台的思维,来解构硬件设计的复杂度。这野心不小,也切中了行业痛点。但芯片行业从来不是一个能“快鱼吃慢鱼”的领域,它信任的是时间、可靠性和最终的产品力。融资近亿只是拿到了入场券,真正的考验在于,他们能否在ARM、Synopsys等巨人的阴影下,证明“AI驱动的芯片设计平民化”不是一个美好的空想,而是可以落地的生产力。市场现在缺的不是概念,而是能把概念焊接到物理世界的能力。隼瞻手里有了资金和一支经验不错的团队,接下来,就看他们如何回答这个最实际的问题了。

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