BearingNAS: Obtaining In-Sensor Intelligent Fault Diagnosis Systems for Bearings Using a Laptop
BearingNAS is a Hardware-Aware Neural Architecture Search (HW-NAS) framework specifically designed for in-sensor processing on extreme micro-budgets (4-8 kiB RAM, 16-32 kiB Flash). The framework utilizes a lightweight, derivative-free search strategy with a decaying kernel growth formulation to prevent parameter explosion, allowing it to run entirely on a laptop CPU in under an hour without discrete GPUs. Evaluated on the CWRU bearing benchmark, the optimized architecture deployed on the STMicro
Analysis
TL;DR
- BearingNAS is a Hardware-Aware Neural Architecture Search (HW-NAS) framework specifically designed for in-sensor processing on extreme micro-budgets (4-8 kiB RAM, 16-32 kiB Flash).
- The framework utilizes a lightweight, derivative-free search strategy with a decaying kernel growth formulation to prevent parameter explosion, allowing it to run entirely on a laptop CPU in under an hour without discrete GPUs.
- Evaluated on the CWRU bearing benchmark, the optimized architecture deployed on the STMicroelectronics LSM6DSO16IS Intelligent Sensor Processing Unit (ISPU) achieved a diagnostic accuracy of 99.50%.
- The research demonstrates the technical viability of shifting machine learning workloads directly into sensor packages, enabling low-cost, production-scale intelligent fault diagnosis.
Why It Matters
This work addresses the critical bottleneck of deploying deep learning models on resource-constrained edge devices by eliminating the need for expensive GPU infrastructure during the architecture search phase. It provides a practical pathway for manufacturers to integrate high-accuracy AI directly into commodity sensors, reducing latency, power consumption, and overall system costs for industrial IoT applications.
Technical Details
- Search Strategy: Employs a derivative-free optimization method paired with a single data-flow search space, utilizing a decaying kernel growth formulation to manage model complexity and avoid parameter explosion within tight memory constraints.
- Hardware Targets: Optimized for three specific STMicroelectronics platforms, including two standard microcontrollers and the LSM6DSO16IS ISPU, which features dedicated hardware acceleration for neural network inference.
- Resource Constraints: Strictly targets embedded memory limits of 4 to 8 kiB of RAM and 16 to 32 kiB of Flash storage, reflecting the physical limitations of modern smart sensors.
- Performance Metrics: Achieved 99.50% accuracy on the Case Western Reserve University (CWRU) dataset, matching or exceeding many larger models while operating within the severe footprint of the target ISPU.
Industry Insight
- Democratization of Edge AI: By removing the dependency on high-performance computing clusters for NAS, companies can adopt advanced model optimization techniques without significant capital expenditure, accelerating the adoption of AI in legacy industrial equipment.
- Shift to In-Sensor Computing: This validates the trend toward moving computation from the cloud or central processors directly to the sensor die, offering a blueprint for other industries requiring real-time, low-power anomaly detection.
- Standardization of Micro-Budget Benchmarks: The use of established benchmarks like CWRU on specialized hardware like the ISPU helps create comparable metrics for evaluating the efficiency of future in-sensor AI solutions.
Disclaimer: The above content is generated by AI and is for reference only.