Hardcore Startup First | Veteran Silicon Photonics Team Raises tens of millions in Angel Round, Targeting Next-Gen CPO/OIO Optical Interconnect Solutions
量引科技完成天使轮数千万元融资，由珠海科技产业集团领投，资金用于团队扩充、迭代流片和补充设备 公司聚焦硅光子传输芯片(PIC)、Optical IO(OIO)及共封装光学(CPO)研发，从核心器件微环调制器(MRM)切入高门槛赛道 自研单通道200G MRM已实现1.6T及更高速率硅基光芯片流片，在国内具有先发优势 掌握底层硅光PDK自研能力，采用成熟且国内自主可控的CMOS工艺节点，规避高端制程供应链风险 已与国内头部GPU厂商达成合作进入PoC阶段，同步推进TSV等3D堆叠先进封装联合研发
Analysis
TL;DR
- 量引科技完成天使轮数千万元融资，由珠海科技产业集团领投，资金用于团队扩充、迭代流片和补充设备
- 公司聚焦硅光子传输芯片(PIC)、Optical IO(OIO)及共封装光学(CPO)研发，从核心器件微环调制器(MRM)切入高门槛赛道
- 自研单通道200G MRM已实现1.6T及更高速率硅基光芯片流片，在国内具有先发优势
- 掌握底层硅光PDK自研能力，采用成熟且国内自主可控的CMOS工艺节点，规避高端制程供应链风险
- 已与国内头部GPU厂商达成合作进入PoC阶段，同步推进TSV等3D堆叠先进封装联合研发
Why It Matters
This represents a critical inflection point in the optical interconnect supply chain as AI compute clusters scale toward 1.6T-3.2T speeds, where traditional pluggable optical modules are hitting physical limits. For AI infrastructure builders and semiconductor investors, domestic silicon photonics capability—particularly in CPO/OIO—becomes a strategic bottleneck and opportunity, especially given the geopolitical context of advanced process access restrictions.
Technical Details
- Core Technology: Micro-ring modulator (MRM) with micron-scale physical footprint and 1V drive voltage, enabling high-density advanced packaging and significantly lower system energy consumption compared to traditional EML or MZM approaches
- Product Roadmap: Self-developed single-channel 200G MRM forming the basis of 1.6T+ silicon photonic chips; full photonic-electronic integration chip combining couplers, waveguides, splitters, and photodetectors (PD)
- Key IP Assets: Real-time temperature control feedback and electrical equalization algorithm IP to address MRM's inherent temperature sensitivity—a major产业化 challenge; wide free spectral range (FSR) micro-ring design enabling dense WDM channel packing without crosstalk
- Manufacturing Strategy: Self-developed silicon photonic PDK (Process Design Kit) rather than relying on foundry-provided PDKs; production via mature, domestically controllable CMOS process nodes to mitigate supply chain risk
- Ecosystem Integration: Collaborating with domestic GPU leaders on CPO/OIO PoC (interface, GPU-optical engine electro-optical signal conversion, protocol adaptation); joint R&D with packaging houses on TSV 3D stacking advanced packaging
Industry Insight
- The CPO-to-OIO transition is becoming a strategic imperative for AI infrastructure; companies that master silicon photonics PDK self-reliance will hold disproportionate leverage in next-gen data center interconnect architecture—watch for consolidation around foundry partnerships vs. independent PDK players
- Domestic Chinese silicon photonics is at an early but accelerating stage; the convergence of GPU厂商 collaboration, advanced packaging co-development, and supply chain localization creates a rare window for Chinese players to establish footholds before global incumbents (Nvidia, Ayar Labs) fully dominate the OIO ecosystem
- The emphasis on MRM over EML/MZM aligns with industry trends from Nvidia, AMD, and Ayar Labs—teams with proven MRM tapeout experience and wide-FSR DWDM capability will be the most valuable partners as OIO moves from lab to production
Disclaimer: The above content is generated by AI and is for reference only.