PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization
PPAPlace introduces a differentiable cross-stage surrogate model that predicts post-route PPA (performance, power, area) directly from macro and standard-cell placements, addressing the near-zero correlation between traditional HPWL optimization and actual post-route timing A label fidelity study across four design flow stages found that post-global-routing labels offer the best balance between timing fidelity and cost-effectiveness, outperforming HPWL and pre-route timing metrics The dual-strea
Analysis
TL;DR
- PPAPlace introduces a differentiable cross-stage surrogate model that predicts post-route PPA (performance, power, area) directly from macro and standard-cell placements, addressing the near-zero correlation between traditional HPWL optimization and actual post-route timing
- A label fidelity study across four design flow stages found that post-global-routing labels offer the best balance between timing fidelity and cost-effectiveness, outperforming HPWL and pre-route timing metrics
- The dual-stream predictor combines graph attention over the chip netlist with spatial convolution over the placement grid, trained on post-global-routing WNS and TNS labels
- PPAPlace operates in two modes: as a co-objective injected into an analytical placer's optimization loop (PPAPlace-CoOpt) and as a post-placement refinement step via projected gradient descent (PPAPlace-Refine)
- On five unseen ChiPBench circuits, PPAPlace improved average WNS by 22% and TNS by 51% over the hierarchical baseline while preserving power and routability, with no test-circuit retraining required
Why It Matters
This work directly addresses a critical failure mode in AI-driven EDA: previous AI placers degraded PPA because they optimized the wrong objective (HPWL), which poorly correlates with final timing. By introducing differentiable cross-stage objectives trained on post-global-routing labels, PPAPlace bridges the gap between early placement decisions and final chip performance, offering a practical path for integrating ML into physical design flows without requiring full post-route simulation during optimization.
Technical Details
- Label Fidelity Study: Evaluated ten circuits at four design flow stages, finding that HPWL and pre-route timing metrics poorly reflect final post-route timing rankings, while post-global-routing achieves the best trade-off between fidelity and computational cost
- Dual-Stream Predictor Architecture: Combines graph attention networks operating over the chip netlist topology with spatial convolutions over the placement grid, enabling the model to capture both connectivity-driven and geometry-driven placement effects
- End-to-End Differentiability: Predicted WNS and TNS gradients flow back to cell coordinates, enabling gradient-based optimization of placement positions through the surrogate
- Two Optimization Modes: PPAPlace-CoOpt injects the timing surrogate as a co-objective within an analytical placer's optimization loop, while PPAPlace-Refine applies projected gradient descent to adjust macro positions after initial placement
- Evaluation: Tested on five ChiPBench circuits excluded from training, achieving 22% WNS and 51% TNS improvement over the hierarchical baseline with zero retraining on test circuits
Industry Insight
- The near-zero HPWL-to-post-route-timing correlation exposed by this work suggests the EDA community should reconsider HPWL as the default placement objective, especially as AI-driven placers become more prevalent
- Using post-global-routing labels (rather than pre-route metrics) for training cross-stage predictors represents a practical sweet spot—offering sufficient fidelity without the prohibitive cost of full post-route timing analysis
- The zero-shot generalization across unseen circuits demonstrates that differentiable surrogates can generalize beyond training distributions, a crucial property for real-world chip design where each circuit is unique
Disclaimer: The above content is generated by AI and is for reference only.