PICasso: An AI-Enabled Design Framework for Autonomous Optimization of Silicon Photonic Devices
PICasso is an AI-assisted framework that automates the synthesis, verification, and optimization of photonic integrated circuits (PICs) directly from natural-language specifications The framework implements a structured NL → YAML → GDS generation pipeline with PDK-aware knowledge injection, automated placement/routing, DRC/LVS validation, and SAX-based photonic simulation PIC-Set, a new benchmark of 36 parameterized PIC design tasks, is introduced to systematically evaluate AI-driven photonic de
Analysis
TL;DR
- PICasso is an AI-assisted framework that automates the synthesis, verification, and optimization of photonic integrated circuits (PICs) directly from natural-language specifications
- The framework implements a structured NL → YAML → GDS generation pipeline with PDK-aware knowledge injection, automated placement/routing, DRC/LVS validation, and SAX-based photonic simulation
- PIC-Set, a new benchmark of 36 parameterized PIC design tasks, is introduced to systematically evaluate AI-driven photonic design under a unified protocol
- PICasso achieves structural Spec@3 of up to 92.7% and functional Spec@3 of up to 52% on high-complexity circuits, significantly outperforming vanilla LLM generation
- Simulation-guided optimization reduces mean circuit insertion loss from 4.98 dB to 3.25 dB (1.74 dB improvement), producing manufacturable layouts with competitive runtimes versus manual GUI workflows
Why It Matters
This work represents a significant step toward autonomous AI-driven hardware design, demonstrating that LLMs can be transformed from brittle text generators into practical design agents when coupled with domain-specific constraints, physical verification, and simulation feedback loops. For AI practitioners and EDA researchers, it establishes a reusable blueprint for grounding generative models in physical simulation and manufacturing constraints—a pattern that generalizes to other domains like electronic IC design and antenna engineering.
Technical Details
- Pipeline Architecture: PICasso implements a three-stage generation pipeline converting natural language specifications into YAML intermediate representations and finally into GDSII layout files, with PDK (Process Design Kit) aware knowledge injection at each stage to ensure manufacturability
- Verification & Simulation Stack: The framework integrates automated placement and routing, Design Rule Check (DRC) and Layout vs. Schematic (LVS) validation, and SAX-based photonic simulation to close the loop between design intent and physical performance
- PIC-Set Benchmark: A curated benchmark of 36 parameterized PIC design tasks covering core photonic primitives (splitters, couplers, bends) and multi-component circuits, evaluated under a unified protocol with novel metrics including structural Spec@k, functional Spec@k, optimization efficiency, and robustness under perturbations
- Performance Results: Across multiple state-of-the-art LLMs, PICasso significantly improves end-to-end specification satisfaction; structural Spec@3 reaches 92.7% and functional Spec@3 reaches 52% on high-complexity circuits, with consistent insertion loss reduction from 4.98 dB to 3.25 dB through simulation-guided iterative optimization
Industry Insight
- The PICasso framework validates a generalizable pattern for AI-driven EDA: coupling LLMs with domain-specific knowledge injection, formal verification, and simulation feedback can overcome the brittleness of raw generative models, making autonomous hardware design increasingly viable for industrial adoption
- The introduction of Spec@k metrics and perturbation robustness evaluation provides a new standard for assessing AI design agents beyond accuracy, emphasizing reliability under real-world variability—a critical consideration for manufacturing deployment
- As PICasso demonstrates competitive runtimes relative to manual GUI-based workflows, it signals that AI-augmented photonic design could reach production readiness within the next few years, potentially disrupting traditional photonic engineering pipelines and reducing time-to-market for custom photonic circuits
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